Reconfigurable System on Chip (822H1)
Reconfigurable System on Chip
Module 822H1
Module details for 2025/26.
15 credits
FHEQ Level 7 (Masters)
Module Outline
This module introduces reconfigurable electronics, such as FPGAs, and their use to realise "Systems on Chip": digital circuits that comprise a multitude of functions such as processors, memories, digital logic, and peripheral interfaces, all realised on a single silicon chip. The module will show for which types of applications a System on Chip approach is beneficial. Students will learn the methodology used to design a system in, for example, VHDL or Verilog (industry standard hardware description languages) and translate it to a functional circuit on an FPGA including testing using state-of-the-art industrial electronic design automation (EDA) tools. This module requires prior knowledge of digital electronics.
AHEP4 LOs: M1, M2, M3, M4, M5, M6, M7, M12, M13, M17
Module learning outcomes
Develop conventional design circuits in reconfigurable chips, such as FPGAs, enabling highly accurate and efficient solutions for real life problems.
Design reconfigurable systems on a chip using a top-down design flow with state-of-the-art EDA tools used both in academia and industry.
Implement a reconfigurable SoC optimised with hardware and software co-design.
Develop a plan to re-design a SoC analysing its lifecycle impact considering factors such as carbon footprint and energy efficiency.
| Type | Timing | Weighting |
|---|---|---|
| Coursework | 100.00% | |
| Coursework components. Weighted as shown below. | ||
| Report | T2 Week 11 | 100.00% |
Timing
Submission deadlines may vary for different types of assignment/groups of students.
Weighting
Coursework components (if listed) total 100% of the overall coursework weighting value.
| Term | Method | Duration | Week pattern |
|---|---|---|---|
| Spring Semester | Laboratory | 4 hours | 11111111111 |
How to read the week pattern
The numbers indicate the weeks of the term and how many events take place each week.
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